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The Geometrical Effects of Bumps on the Fatigue Life of Flip-chip Packages by Taguchi Method
Wen-Ren Jong
Department of Mechanical Engineering Chung Yuan Christian University Chung-Li, 32023 Taiwan, ROC; wenren{at}cycu.edu.tw
Shia-Chung Chen
Hsin-Chun Tsai
Chien-Chia Chiu
Hsiu-Tao Chang
Department of Mechanical Engineering Chung Yuan Christian University Chung-Li, 32023 Taiwan, ROC
This study employs the coupled field method of thermal analysis with the structural method to simulate the thermal conduction and mechanical behaviors of flip-chip packages. The full, one-quarter symmetrical, one-eighth symmetrical, and stripped finite element models are analyzed by thermal shock test in the temperature loading range of 55–125° C. Engelmaier's model is used to study the issues of fatigue life of these models. The results reveal that the one-eighth symmetrical model can save CPU time, and still retain the accuracy of analysis. Furthermore, this study investigates the geometrical dimensions of bumps regarding the effects and the reliability of flip-chip bumps by means of one-eighth symmetrical finite element model with CAE analysis under the loading of cyclic temperature. The Taguchi method is employed to find the optimum upper diameter, lower diameter, height, and width of bumps in this research. There is a novel concept that the climbing height of underfill is considered as the noise factor since it has an impact on the fatigue life of flip-chip packages. Analysis of variance is used to examine the contribution of these geometric parameters with respect to fatigue life of solder bumps. It is found that the influence of climbing height of underfill is more significant on the fatigue life of flip-chip bumps and the width of the solder bump is the most important factor.
Key Words: flip-chip • underfill • fatigue life • Taguchi method
References
- Lau, J. H. and Pao, Y. H. (1997). Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, NY.
- Wang, J., Qian, Z., Zou, D. and Liu, S. (1998). Creep Behavior of a Flip-Chip Package by Both FEM Modeling and Real Time Moire Interferometry, Transactions of the ASME Journal of Electronic Packaging, 120(2): 179–185.
- Teo, K. H. (1998). Reliability Assessment of Flip Chip on Board Connections, Proceedings of the IEEE/ CPMT 2nd Electronics Packaging Technology Conference (EPTC’98), pp. 269–273.
- Darbha, K., Okura, J. H., Shetty, S. and Dasgupta, A. (1999). Thermomechanical Durability Analysis of Flip Chip Solder Interconnects: Part 1-Without Underfill, Transactions of the ASME Journal of Electronic Packaging, 121(4): 231–236.
- Darbha, K., Okura, J. H., Shetty, S. and Dasgupta, A. (1999). Thermomechanical Durability Analysis of Flip Chip Solder Interconnects: Part 2-Without Underfill, Transactions of the ASME Journal of Electronic Packaging, 121(4): 237–241.
- Pang, J. H. L., Chong, D. Y. R. and Low, T. H. (2001). Thermal Cycling Analysis of Flip Chip Solder Joint Reliability, IEEE Transactions on Components and Packaging Technology, 24(4): 705–712.[CrossRef]
- Knecht, S. and Fox, L. R. (1990). Constitutive Relation and Creep-Fatigue Life Model for Eutectic Tin-Lead Solder, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 13(2): 424–433.
- Engelmaier, W. (1983). Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling, IEEE Transactions on Components, Hybrids and Manufacturing Technology, CHMT-6(3): 232–237.[CrossRef]
- Hwang, J. S. (1992). Solder Paste in Electronics Packaging, Van Nostrand Reinhold, New York.
- Hong, B. Z. and Su, L. S. (1998). On Thermal Stresses and Reliability of a PBGA Chip Scale Package, Proceedings of the 48th Electronic Components & Technology Conference, pp. 503–510.
- ANSYS (2003). Nonlinear Structural Analysis, ANSYS Users’ Manual 7.1.
- Lau, J. H., Lee, S. W. R., Pan, S. H. and Chang, C. (2002). Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications, Transactions of the ASME Journal of Electronic Packaging, 124(3): 205–211.
- Chang, J. N., Luo, S. J., Sung, C. C., Kaou, S. L., Tsai, C. W., Chen, S. L., Chuang, T. S. and Chiu, J. H. (1999). Introduction of Taguchi Quality Engineering, R.O.C. Quality Control Association, Taiwan.
- Lee, H. H. (2000). Taguchi Methods: Principles and Practices of Quality Design, Gauli, Taipei, Taiwan.
- Pang, J. H. L., Tan, T. I. and Sitaraman, S. K. (1998). Thermo-Mechanical Analysis of Solder Joint Fatigue and Creep in a Flip Chip on Board Package Subjected to Temperature Cycling Loading, Proceedings of the 48th Electronic Components & Technology Conference, pp. 878–883.
Journal of Reinforced Plastics and Composites, Vol. 25, No. 1,
99-114 (2006)
DOI: 10.1177/0731684406055459
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